The Lyceum: Semiconductor Weekly — Apr 15, 2026

ASML and TSMC reported within hours of each other, and the combined picture is unambiguous: the AI infrastructure buildout is accelerating faster than either the world's only EUV lithography maker or the world's only leading-edge foundry can grow. ASML raised full-year guidance to €36–40 billion while China's share of its system sales collapsed from 36% to 19% in a single quarter — the clearest proof yet that export controls are physically rerouting where advanced chips get made. TSMC posted $35.7 billion in Q1 revenue, a foundry record, with many wafers already committed, per the company. The constraint isn't demand anymore; instead, constraints are increasingly physical, geographic, and in advanced packaging — the step most people still ignore.

• Mitsubishi Electric Fukuoka Power Semiconductor Plant (Mitsubishi Electric): New SiC power semiconductor fab completed in Fukuoka, Japan; operations slated for October 2026 with automation targeting ~40% productivity gains over prior lines.
• ASE Renwu Test Facility Groundbreaking (ASE Technology): Broke ground on dedicated wafer and chip testing cluster in Kaohsiung, Taiwan; Phase I operations targeted for April 2027, creating 1,000+ jobs.
• JSR CMP Material Development Center — Taiwan (JSR Corporation): Opened CMP slurry R&D center in Hsinchu Science Park to co-develop planarization materials with TSMC for N3/N2 process ramps.

ASML reported Q1 net sales of €8.8 billion, a 53% gross margin, and €2.8 billion in net income — then raised its full-year 2026 revenue guidance to €36–40 billion, up from €34–39 billion. Those are good numbers. They are not the important number.

The important number is 19%. That's China's share of ASML system sales in Q1, down from 36% just one quarter earlier. South Korea surged to 45% from 22% over the same period, according to ASML's Q1 slides. That isn't a gradual drift — it's a cliff, and it coincides with tightening DUV export controls. The lithography capacity China was absorbing now appears to be flowing to SK Hynix and Samsung as they race to build HBM4 production lines.

The end-market mix flipped too: memory applications rose to 51% of system sales from 30% in Q4, while logic fell to 49% from 70%. Memory is now the dominant buyer of new lithography tools — a reversal from the logic-heavy mix of the past two years. ASML said on its earnings call that customers have increased expected demand and are accelerating capacity expansion plans. That statement suggests fab investment decisions may be locked in through 2027.

One stealth capacity expansion worth noting: ASML has pushed throughput on its NXE:3800E EUV system to 220–230 wafers per hour, and demonstrated a 1,000-watt EUV source that supports a path to 330 wafers per hour by 2031. That's effectively free capacity for every fab that already owns one — thousands of additional wafer starts per month at TSMC's scale without a single new tool shipment.

If ASML's Q2 guidance of €8.4–9.0 billion holds, the Korea/Taiwan ramp is compensating for the China demand hole. If it softens, the hole is bigger than the ramp can fill. That's your signal.

TSMC reported Q1 2026 revenue of $35.7 billion — up 35.1% year-on-year, a new quarterly record, and a beat against consensus. March alone hit NT$415.2 billion ($13.1 billion), the strongest single month in TSMC's history, according to Vucense's analysis. Growth came amid strong demand for high-performance computing chips for AI data centers — with Nvidia and Broadcom among the largest customers — alongside Apple's custom silicon. TSMC also raised advanced-node pricing 5–10% at the start of the year, part of a four-year plan of consecutive increases for processes below 5nm.

The company is spending $52–56 billion on capex in 2026, almost entirely on leading-edge nodes. Its board approved a capital injection of up to $30 billion to TSMC Global for capacity expansion, per TSMC's board filing. TSMC said many wafers are already committed. AI chip supply constraints may persist this year even with increased hyperscaler spending.

Macquarie analysts have warned that margins may have peaked in Q1 as 3nm expands and 2nm enters mass production — 2nm depreciation costs are real and front-loaded. The full earnings call on April 16 will reveal gross margin, Q2 guidance, and any update on N2 yield and Arizona timelines. If TSMC raises its 30% full-year growth guidance, equipment vendors should update their WFE models immediately. If it doesn't, the margin peak thesis gets louder.

SK Hynix reported Q1 operating profit of 7.44 trillion won ($5.2 billion), up 157.8% year-on-year, beating consensus of 6.75 trillion won and — notably — exceeding Samsung's Q1 semiconductor operating profit of 6.6 trillion won. The outperformance came largely from 12-layer HBM3E memory chips used in training large language models. SK Hynix is the top supplier of advanced AI memory to Nvidia.

The forward signal matters more than the backward-looking number. SK Hynix expects HBM shipments to double this year, locked in through contracts agreed a year in advance. The company has already delivered samples of its sixth-generation HBM4 memory to key customers — the world's first to do so — and plans to complete mass production preparations for 12-layer HBM4 by year-end.

SK Hynix's operating margin hit 42% in Q1, continuing an eight-quarter streak of sequential improvement. Eight consecutive quarters of margin expansion at a memory company — historically one of the most cyclical businesses in semiconductors — is the clearest evidence that HBM has fundamentally changed the economics of the memory industry. HBM4 qualification timelines are now the single most important variable in the AI accelerator supply chain for 2027. Samsung is fighting to close the gap, but SK Hynix's head start in customer qualification doesn't close overnight.

Samsung's semiconductor division posted Q1 operating profit of approximately 6.6 trillion won — solid, but below SK Hynix's 7.44 trillion won, reflecting Samsung's slower HBM3E ramp and ongoing yield challenges. Simultaneously, Samsung's union is escalating a dispute over performance bonuses, demanding a larger share of record profits and threatening strike action. Korean news outlet Nate reported potential losses of up to 10 trillion won from a strike.

The timing is brutal. Samsung is ramping HBM4 production, qualifying its 2nm gate-all-around process for external foundry customers, and trying to close the gap with SK Hynix in AI memory market share. A production disruption at Pyeongtaek — Samsung's largest and most advanced fab campus — would ripple directly into Nvidia's Rubin GPU supply chain. Korean media also report the DX division has initiated voluntary retirement programs even amid record performance, signaling internal restructuring tensions beyond the union dispute.

A Samsung fab strike in 2026 isn't a labor story — it's an AI supply chain story. If the union escalates to a vote or action deadline at Pyeongtaek, treat it as a Tier 1 supply event. If management resolves it quickly, Samsung's HBM4 ramp stays on track. Watch Korean labor news weekly.

TSMC's CoPoS (Chip on Panel on Substrate) pilot line is set for completion by June, with volume production expected between 2028 and 2029, according to Commercial Times reporting via TrendForce. CoPoS replaces the round silicon wafer interposer in today's CoWoS-L — the advanced packaging that bonds GPU dies to HBM stacks — with a rectangular panel format. Think switching from a circular pizza stone to a rectangular baking sheet: better material utilization, higher throughput, and a path toward glass substrates.

This matters because CoWoS capacity is already the single biggest constraint on AI accelerator shipments. Advanced packaging accounted for roughly 8% of TSMC's revenue in 2025 and is expected to surpass 10% in 2026. CoPoS is the architecture that could eventually break the packaging bottleneck at scale. But the pilot line completion is a process qualification milestone, not a production ramp — and the gap between those two things is where most semiconductor timelines slip.

Supply chain sources cited by TrendForce caution that warpage issues intensify as substrate sizes expand, emerging as one of the biggest hurdles to mass production. Panel-level packaging has been "two years away" for most of this decade, and the physics of keeping a large flat substrate from bowing during thermal cycling is genuinely hard. The June pilot completion date is the number to track. If it slips, the 2028 ramp target slips with it.

The Commerce Department's Section 232 investigation into semiconductor imports — Section 232 of the Trade Expansion Act of 1962 — has moved from theoretical to operational. A Federal Register notice invites comments on imports of semiconductors, manufacturing equipment, and — critically — "derivative products," explicitly asking about domestic demand by node, the role of foreign fabs and OSAT operations, and U.S. dependence on imported tools and chips.

Section 232 is the same national-security trade mechanism used for steel and aluminum tariffs. Once semiconductors and derivative products are inside that frame, the question shifts from "should there be more domestic capacity?" to "which imports get tariffed, when, and how broadly?" The derivative-product language could pull in everything from substrates to finished systems.

The April 14 deadline for the Commerce Secretary's 90-day Phase 1 negotiation report passed yesterday with no public announcement. A clean outcome would likely have been announced. The silence suggests either unresolved negotiations or a broader tariff action being prepared. The next hard deadline is July 1, when Commerce must update the President on the data center semiconductor market. If BIS receives a flood of detailed industry comments, treat it as evidence companies are modeling tariff risk operationally, not politically.

The EU Chips Act promised €43 billion for European semiconductor sovereignty. EE Times published a detailed analysis this week of how that money actually flows, and the picture is sobering. The headline number mixes public grants, state aid, equity investments, and loan guarantees — not all fungible or deployable at fab-construction speed. Intel's planned Magdeburg fab remains in a holding pattern during Intel's financial restructuring. TSMC's Dresden joint venture (with Bosch, Infineon, and NXP) is on track but targets 28nm/22nm specialty nodes for automotive — trailing-edge, not leading-edge.

The European Commission signaled it's moving toward a pragmatic rewrite: an implementation dialogue toward a "Chips Act 2.0" that could shift funding toward pilot lines, packaging, power semiconductors, and equipment rather than trying to replicate an Asian foundry ecosystem wholesale. If Brussels follows through, it would be a necessary course-correction from headline pledges to deliverable industrial capability.

Europe is building trailing-edge resilience while the leading-edge gap widens. If Intel Foundry's European timeline extends further, the continent's leading-edge ambitions effectively depend on attracting TSMC or Samsung — neither of which has announced plans for sub-7nm European capacity. Watch Intel's restructuring updates as the proxy.

• Mitsubishi Electric Fukuoka SiC Fab: Construction complete on a power semiconductor plant in Fukuoka targeting SiC devices for EV inverters and renewable energy systems. Automation upgrades aim for ~40% productivity improvement over prior lines; operations begin October 2026. This directly addresses the SiC supply gap that's been constraining next-gen EV traction motor sourcing.
• ASE Renwu Hi-Tech Testing Cluster: ASE broke ground on a dedicated wafer and chip testing facility in Kaohsiung's Renwu Industrial Park. Phase I targets April 2027 with 1,000+ jobs. The emphasis on testing — not just assembly — reflects the growing validation burden of multi-die AI packages where test time and failure analysis are becoming first-class constraints.

China's share of ASML's order book fell off a cliff in one quarter; TSMC posted a month so strong it needed a new column in the spreadsheet; and Samsung's workers looked at record profits and said where's ours?

Somewhere in Hsinchu, a JSR engineer is polishing a wafer with a slurry recipe that took 23 hours to iterate instead of three weeks — and that's quietly worth more to the AI buildout than most billion-dollar announcements.

Eyes on the fabs.

If someone you know is making sourcing decisions, forward this before they find out the hard way.

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